(This column, which originally appeared in Global SMT & Packaging magazine 6.1 (Jan 2006), is also available as a free PDF.) 

Over the last couple of weeks, I have been inundated with items relating to voids in solder joints[1-4]. In the first article, in the September issue of GSMT&P, Dongkai Shangguan of Flextronics discusses some of the processes and mechanisms active in the formation of voids in solder joints. In the second reference, NPL in the UK announces that voids in solder joints have no effect on either the fatigue reliability or the shear strength of solder joints deliberately produced with voids. In the third, Jack Crawford of the IPC relates the ‘heated’ committee discussion on the level of voiding to be allowed in IPC specifications, during an IPC TechNet Forum discussion on voids. And lastly, an article in Assembly on micro-voids , by Donald Cullen of MacDermid, states that “…all solder voids…are troublesome when they exist in sufficient number to reduce the cross-sectional area of the joint.”

The current IPC-610-D[5] specification allows a maximum of 25% voiding by area; IPC-7095[6] recommends for Class 3 product a maximum of 9% voids by area (=30% of solder ball diameter) in BGA solder joints and 20% voids by area (=45% of solder ball diameter) for Class 2 product.
In the NPL study involving seven different LF-solder pastes, no void level exceeding 15% in any PBGA solder joint could be produced despite efforts to produce higher void levels. (More details are available in reference 7.) These voids produced “…no adverse effect on reliability…[and] the shear strength, was…unaffected.”

Voids have been of significant interest for some time—in my opinion, however, they have received more attention than they deserve. As is stated in IPC-7095[6], “There is no evidence or empirical data that indicates that voids within the ball will cause failure.” This corresponds completely with my experience. Thus, the question arises: “Why all this attention?” One reason might be that voids are easily seen in non-destructive x-ray examinations (Figure 1). So, now you have this information, obtained with a rather expensive piece of equipment, and the question arises: what do you do with it?

Figure 1:    X-ray image of voids in BGA solder joints. [Source: IPC-7095A, Ref.6].

Let’s first define the main categories of voids. The main differentiation is by size, into macro- and micro-voids, and then by their source or mechanism of creation: inclusion and shrinkage voids for the macro-void category, and Kirkendall and ‘Champagne’ voids for the micro-sized ones. The two types of macro-voids are illustrated in Figures 2 and 3. The voids formed by the inclusion of volatiles, perhaps from flux, have a typical, relatively spherical, smooth-walled appearance, as shown in Figure 2, whereas shrinkage voids, which form in areas in solder joint interiors that solidify last and where the available solder volume is smaller than the geometric volume that needs to be filled. They are characterized by an irregular ‘crystalline-like’ appearance, as shown in Figure 3.

Figure 2:    Macro-voids formed by the inclusion of volatiles.
[Source: Werner Engelmaier, Bell Telephone Laboratories, USA].

Figure 3:    Macro-voids formed by the shrinkage of liquid solder on cooling and solidification.
[Source: Werner Engelmaier, Bell Telephone Laboratories, USA].

Figure 4:    Kirkendall voids formed in a SAC lead-free solder joint at the copper
pad/intermetallic layer interface. [Source: Tz-Cheng Chiu et. al., TI, USA, Ref. 9].

Kirkendall voids have been observed in the laboratory for both SnPb and LF-solder; however, there is no documented evidence of a field failure due to Kirkendall voids in the whole history of surface mount technology.

‘Champagne’ voids are formed at or near the interface of the solder joint and the soldering metallization, typically of the PCB. They can form due to reflow soldering temperatures being too low to facilitate their escape. In other instances they occur because metallization layers, like immersion Ag, are too thick; however, efforts to produce ‘champagne’ voids required a ‘Perfect Storm’ of a combination of parameters in extremis[4]. Figure 5 shows ‘Champagne’ voiding in a lead-free solder joint.

Figure 5:    ‘Champagne’ micro-voids in both SEM (top-down) and cross-section
views voids. [Source: Donald P. Cullen, MacDermid, USA, Ref. 8].

Effect of Voids.

There is the myth floating about that macro-voids stop or slow down cracks in solder joints, a la the Liberty Bell crack. It most likely stems from some work Chuck Schmidt did at SRI (Stanford Research Institute) where he found that indeed in the vicinity of a void the propagation of the crack front was retarded. But this effect was highly localized, and as soon as the crack front progressed beyond the void, the retarded portion of the crack front rapidly caught up with the rest.

As is stated in IPC-7095[6]: “There is no evidence or empirical data that indicates that voids within the ball will cause failure.” Failures relating to solder joints with voids are anecdotal and have not been subjected to a documented root-cause analysis. This is true for macro-voids. There is the possibility of a slight increase in creep-fatigue reliability if the macro-voids increase the solder joint height; however, whatever effect may occur, it would hardly be significant.
On the other hand, voids in ‘incoming’ solder balls can have a negative impact on reliability, if the reduced solder volume causes more of a collapse of the solder joints.

Until recently, no documented failures due to micro-voids have been reported. However, in reference 4 it is stated, that “micro-voids and immersion silver was prompted by the high-visibility failure of a ball grid array (BGA) on a PCB during post-assembly power cycling.”

Also, the formation of micro-voids by Kirkendall voiding has been found to reduce drop resistance of solder attachments. At this time Kirkendall voiding depends on an as yet unknown combination of factors, which at least include long-term exposures to elevated temperatures of about 100°C or higher. It should be noted that Kirkendall voiding appears to occur more readily with Pb-free solders.

References:
[1]    Shangguan, Dongkai, “Voids in Solder Joints,” Global SMT & Packaging, Vol. 5, No. 8, September 2005, p. 47.
[2]    “NPL Release Report on Effect of Voiding on Lead-Free Reliability,” NPL Press Release, National Physical Laboratory, Teddington, UK, September 30, 2005.
[3]    I-Chat Exchange with Jack Crawford, IPC, October 7, 2005.
[4]    Cullen, Donald P., “Avoiding Microvoids,” Assembly, September 2005.
[5]    IPC-610, Rev. D, “Acceptability of Electronic Assemblies,” February 2005.
[6]    IPC-7095A, “Design and Assembly Process Implementation for BGAs,” October 2004.
[7]    Wickham, M., M. Dusek, L. Zou and C. Hunt, “Effect of Voiding on Lead-Free Reliability,” NPL Report DECP MPR 033, National Physical Laboratory, Teddington, UK, April 2005.
[8]    Cullen, Donald P., “Characterization, Reproduction, and Resolution of Solderjoint Microvoiding,” Proc. Elec. Circuit World Conf., Anaheim, CA, February 2005.
[9]    Tz-Cheng Chiu, et.al., “Effect of Thermal Aging on Board Level Drop Reliability of Pb-Free BGA Packages,” Proc. 2004 ECTC, pp.1256-1262.

Werner Engelmaier has over 40 years experience in electronic packaging and interconnection technology. Known as ‘Mr. Reliability’ in the industry, he is the president of Engelmaier Associates, L.C., a firm providing consulting services on reliability, manufacturing and processing aspects of electronic packaging and interconnection technology. He is the chairman of the IPC Main Committee on Product Reliability. He was elected into the IPC Hall of Fame 2003, and was awarded the IPC President’s Award in 1996 and the IEPS Electronic Packaging Achievement Award in 1987. He also was named a Bell Telephone Laboratories Distinguished Member of Technical Staff in 1986 and an IMAPS Fellow in 1996. More information is available at www.engelmaier.com, and he can be reached at engelmaier@aol.com.

Keywords : Engelmaier, voids, solder joints, micro-voids, macro-voids

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