Memory is vital to virtually all electronic systems of any complexity. In the world of semiconductors memory comes in many forms; among those are SRAM, Flash, MRAM and perhaps the most ubiquitous of all, DRAM. After local cache memory on or in the processor package assembly, DRAM is the memory technology that is used almost exclusively for direct communication with the CPU. Workhorse that it is, DRAM is nevertheless a key and gating technology to the overall performance of electronic computing systems because memory deployed in its current form is significantly slower that the microprocessor. For instance, while leading edge processors are now operating at 4GHz, present generation memory is only capable of 400 MHz performance. This disparity results in a condition generally referred to as the ‘memory bottleneck’. In such condition, the CPU must remain in a wait state until the memory data is written or retrieved. The problem has been addressed, in part, by improved memory system designs. However, as electronic systems move into the multi-gigabit per second data rate range, a significant gap remains between top-end operating rates of CPU ICs and memory ICs. Part of this ongoing disparity is due to the limits of current interconnection design, which often results, particularly at higher frequencies, in disturbances that contribute to signal distortion. For example, signal distortion can often be due, at least in part, to so-called parasitic effects resulting from traditional interconnect designs. Because signal speed and signal integrity are two primary goals in digital signal transmission, interconnect designs that assure signal integrity during data transmission are key. Controlling signal integrity begins with the design of the circuit. Choices made in terms of circuit layout, and the materials used and the general architecture of the complete assembly, will all have impact of the quality if the signal transmission and its ultimate integrity.

Parasitic effects associated with packaging and interconnections and signal discontinuity are primary sources of signal disturbance, thus one of the major objectives when tasked with maintaining signal integrity is to eliminate or minimize the parasitic effects and electrical discontinuities impinging upon a signal. Parasitic effects and electrical discontinuities are caused by a number of factors, such as sharp changes in direction, changes in material, circuit feature flaws and even interconnections, such as solder balls used to connect IC packages to next level interconnection substrates. All these can affect signal integrity by introducing undesirable changes in impedance and creating signal reflections. There is also concern about signal skew, caused by differing signal lengths, which is important in assuring proper signal timing. Finally, cross talk between signals due to inductance is another deleterious effect associated with current packaging structures for memory ICs.

The first place in an electronic system such parasitic effects are encountered, (beyond those encountered within the IC’s interconnection structure itself) is the IC package that is used to connect the IC die to a next level interconnection system. While current generation IC packages are presently reasonably well suited to meeting current needs, as the electronics industry moves to ever higher data signaling rates, the formerly minor concerns associated with packages and interconnection paths have now reached a level of critical importance.

The net effect of this complex web of interactive elements is that they collectively combine to make it extremely difficult to predict and design for reliable high performance at higher processing speeds. Additionally, at higher processing speeds, parasitic effects and signal discontinuities and reflections can contribute to the thermal demands placed on a system. Thus, as memory circuit speeds climb, there is need for new approaches to the design of memory package interconnections to overcome the looming and highly complex electrical and thermal problems associated with traditional approaches to IC memory packaging and to create structures that require lower power to operate. Moreover, there is need to identify and deploy IC packages for memory devices that are high yielding in manufacture and assembly and are inexpensive to build and use.

In response to this challenge, a couple of new memory packaging concepts are presently in early stage joint development by a group of leading edge companies. One of the first concepts is predicated on the stair step concept described in an earlier column. Several memory die are interconnected side by side within the package, and the high speed memory bus between the ICs is kept within the package rather than ‘porpoising’ in and out of the DIMM module through a series of solder balls. The bus is simply terminated at both ends of the memory strip. The memory die can be placed individually within the package as shown in Figure 1, or going forward it may be of value to dice the chips out in strips, provided the yield is predictably high enough after burn in. The basic package structure is shown in both exploded and assembled form in Figure 1.

Figure 1. Example of elements of construction and finished memory package strip.
The multiple pieces of top layer circuits can be replaced by a single strip for simplicity.

While the just described assembly represents more of a futurist view of memory packaging, a more practical and near term concept that is also based on the stair step concept and the elimination of plated vias is shown in Figure 2. A metal plane is provided within the package and serves as a ground to help mitigate the effects of lead inductance that increases with increasing signal speed. It also helps to better control the characteristic impedance of the package.

Figure 2. Example of two metal memory package having no plated through vias.

In summary, a linear path forward in terms of memory packaging and interconnection is likely to lead to a dead end. As a result, a more thoughtful look forward is required. Bridging technologies to the future cannot (or at least should not) be developed and deployed at the last minute with any confidence of success, thus efforts to develop solutions in advance of the problem are required to assure a trouble free transition into the future. In the end it comes down to a question of one either being actively involved in shaping the future or simply conforming to whatever solutions may come.

This column appeared in Global SMT & Packaging magazine issue 7.2 - February 2007.

Keywords : Fjelstad, memory, SRAM, Flash, MRAM, DRAM

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