During the week of October 30th through November 3rd 2006, I had the good fortune to attend two excellent conferences, one in Asia the other in San Jose, California. The first was the 6th Annual International Workshop on Microelectronics Assembly and Packaging (MAP) held Oct 30 - Nov 1, 2006 in Fukuoka, Japan, and organized by Professor Hajime Tomokage of Fukuoka University and his committee members as well as by JETIA, JETRO and a number of local government agencies. The other event was the 3rd annual International Wafer Level Packaging Congress (IWLPC) organized by the Surface Mount Technology Association (SMTA) and ChipScale Review, held November 1 - 3 2006. Both events were exceptionally well organized and well attended.

Looking first to MAP 2006, this is the second time I have had the honor to attend the MAP event, this year as an invited speaker in the opening session. It has been mostly a regional event in past years with most participants coming from Asia; however this year saw increased participation from North America and Europe. The official language for the conference is English, which has become the default language for business. This made access to the information very easy for me. The level and quality of the papers presented were quite high and included presentations on research from universities in Japan and Korea. Topics included system in package and embedded device technologies, wafer level processing, advanced materials and package structures, MEMS and fine interconnection technologies, testing, analysis and inspection equipment and system integration technologies. A small trade show compliments the conference.

While I was not able to participate in the tour, due to my travel plans, facility tours on the third day are a part of the program and are very popular with attendees. Last year the visits were to Panasonic and Toyota, and this year it was NEC Semicon Package Solutions Oita Plant. I plan to attend next year’s event, and as I have been invited to serve ad a member of the organizing committee, I hope to successfully solicit papers from Europe and North America. If interested, please visit the link provided in the references.
 
The second event attended during a busy week was the IWLPC. This year’s event was the best one yet, in my opinion. One of the most refreshing aspects was the lack of lead-free papers. With the hyperbole surrounding lead-free now moving off center stage, attention is shifting back to where it should have been for the last several years, and that is on innovation. Thus with lead-free gone, there were many excellent and very interesting papers and invited talks made this year.

The venue, which included both papers and table top exhibits, was graced by the attendance of many packaging industry luminaries, including several well known analysts and researchers. Electronic Trend Publications’ Sandra Winkler, Jan Vardaman of TechSearch International, Gartner Dataquest’s Jim Walker, Morry Marshall of Semico Research and Dr. George Riley of Flip Chips Dot Com were all present, and each gave their views on the business and marketing issues surrounding wafer level packaging and IC packaging in general.

The program was co-chaired again this year by the always enthusiastic Dr. Ken Gilleo of ET-Trends, this time ably assisted by a new co-chair, ChipScale Review’s Senior Editor and industry veteran, Terry Thompson. The keynote address was offered up by Wilf Corrigan, founder and retired chairman of LSI Logic. Corrigan provided his historical perspective on the IC industry based on his career, which has spanned more than four decades. His talk was peppered with anecdotes and gems of wisdom he has acquired during those many years in the electronics industry. However, the conference’s main course was the technical papers and panel sessions that were designed to satisfy the technologist’s appetite, and that mission was soundly accomplished.

While there is not space here to summarize all of the papers and panel sessions, there were a few things that stood out in the mind of this reviewer, who admits to a bias for the novel and unusual. Among the stand-outs were two presentations made by Dr. Gilleo. Ken has long demonstrated his own unquenchable appetite for all manner of technology both old and new. His review of MEMS, which he pointed out are almost inevitably packaged on a wafer, also made clear the diversity of the technology and provided insight into the many ways it can be used, beyond simple sensors. Ken also gave his views on the future of electronic interconnection in a later session, where he anticipates that the electron may well be replaced by a photon for all high speed data transmission.

While wafer level may be the linchpin topic for the conference, several 3D packaging solution papers were found in the mix. Wafer stacking, back side via technologies and even papers on making highly flexible IC package structures were provided. In addition to 3D, there were at least two papers that touched on the topic of printing electronic interconnections, one by Associate Professor at Georgia Tech, Engent founder and SMTA director, Dr. Daniel Baldwin, who showed how printed conductor technology could be adapted to ‘chips first’ packaging technology and a second paper by Dr. Bruce King of Optomec that showed an novel aerosol jet-based printing technology that is well suited to 3D printing of silver ink conductors.

There were simply too many excellent papers to mention them all; however if the reader has interest in finding our more about either of these conferences so that they can put them on their calendar for next year, links to this year’s events are provided below. I hope to see you at one or the other next year.

Links:
http://map-and-rts.com/blog1/
http://www.smta.org/iwlpc/

This column appeared in Global SMT & Packaging magazine issue 7.1 - January 2007.

Keywords : MAP 2006, IWLPC 2006, IWPLC, Joe Fjelstad

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