(This column, which originally appeared in Global SMT & Packaging magazine 6.8 (September 2006), is also available as a free PDF.)

Nobel laureate Dr. Richard Feynman is revered by physicists the world over for his contributions to quantum mechanics, and he endeared himself to many nonscientists by his extraordinary ability to make simple and comprehensible matters that might otherwise seem too complex for the average person to grasp. One of the most inspired demonstrations of this ability was during the hearings after the Challenger disaster when Feynman shattered an O-ring made of the same material used on the shuttle’s booster rockets after dipping it in ice water to reduce its temperature to one equivalent to that experienced by the Challenger’s boosters on the day of the tragedy. However, it is a prescient talk Dr. Feynman gave in late 1959, at a meeting of the American Physical Society at California Institute of Technology that truly stands out for the electronics industry. The talk was titled: “There’s Plenty of Room at the Bottom”1, and it is broadly recognized as a talk that crystallized thinking relative to the future of product miniaturization. In his presentation, Feynman questioned what people of the year 2000 might think of the limited efforts at miniaturization that had been done up to that date. He suggested that those in the future might wonder what took everyone so long to get started. He then went on to describe a number of futuristic ideas on miniaturization that have since been realized, the most notable of these being the advances we have seen in computer miniaturization, MEMS and even nanotechnology. Feynman’s early observations in that paper have been getting increased notice in recent years as developers of today’s microelectronics pay homage to man who was well ahead of his time.

Making things smaller has been critical to the success of the electronics industry to date, but how far down can we go before we find bottom? Think now of another revered physicist, Albert Einstein, that great man who offered us another piece of sage advice: “Things should be made as simple as possible but not simpler.” This idea gives rise to a suggested corollary also suited to the challenges faced by microelectronic industry and its products: “Things should be made as small as possible but not smaller.”

As the industry continues to drive down semiconductor feature sizes in an almost religious-like devotion to extending the life of Moore’s Law, the fact, acknowledged by Dr. Moore himself, is that, unlike a true law of physics, Moore’s Law will reach an end point where the lithographic-based reduction of feature sizes that is the foundation of Moore’s predictions must end. We appear to be nearing the point where, as has been cleverly stated in presentations a few times over the last year or so, we will see a reduction in the pursuit of “More of Moore” and an increased effort in areas that offer “More than Moore”. This new “More than Moore” era will be characterized by more appreciation of the volumetric reduction possibilities that lie ahead. This was touched on in a previous column where this emergent era was described as one of volumetric system miniaturization and interconnection/integration or VSMI.

The new era of volumetric miniaturization actually had its beginnings a good number of years ago when some foresighted packaging engineers constrained by space in military electronics and satellite/ aerospace applications developed stack IC packaging technology. Memory was a natural early target but the idea has been extended to a range of mixed technology applications since the turn of the millennium. The result has been an explosion of new IC chip assembly and package structures and constructions. While it might seem that, thematically, there might be very limited number of permutations possible with stacking chips and packages, the actual number and variety packaging innovations that have been described is nothing short of amazing.

Present solutions include mixtures of stacked wire bonded ICs, stacked flip chips that      interconnect by way of back of silicon vias and combinations of flip chip and wire bonded interconnections in a single package. Packages and discrete devices have been placed inside other packages (PiP) and then packages themselves have been stacked (PoP). IC packages have been assembled on flexible base materials and folded into origami-like assemblies. Many of these solutions have evolved in response to the limitations encountered by those in pursuit of system on chip (SoC) solutions which are often stymied by the challenges of making mixed technology (i.e., digital and analog) wafers. The alternative solution to SoC is called system in package (SiP). These solutions however do not mark the end; there is likely to be much more interesting innovation in the future. 

Given the level of innovation and the dynamic changes presently underway, it is almost certain that there will be yet more change ahead. While there are no perfect crystal balls with which to see the future, it is reasonable to expect that IC packaging, which is now the generally acknowledged gatekeeper of performance, will become even more important in the years ahead. The third dimension has just been cracked, and as packaging engineers continue to pry it open to discover what treasures await them there, we are likely to see many new ways of addressing the challenge of electronic miniaturization and realize all the ever-sought benefits that come with it…cheaper, faster, lighter and friendlier to the environment by virtue of the reduced use of raw materials and energy, both in manufacture and in use.

Dr. Feynman was most definitely right. There is “plenty of room at the bottom”, but we should also remain mindful that we should not try to make things “smaller than is possible”…but then again, maybe, just maybe, we should.


References
[1] http://www.zyvex.com/nanotech/feynman.html
 

Keywords : Fjelstad, Microelectronic miniaturization, PiP, PoP, SoC, SiP

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